AMBA APB1 to APB4 changes

The original APB specification uses PSTB as well as BCLK to capture signals. It allows write capture on the rising edge of PSTB, the falling edge of PSTB, or the rising edge of BCLK while PSTB is HIGH.

Now, if peripherals are designed to operate on one of these edges while the system bus uses a different timing convention, we need to adapt the bridge for compatibility.

APB2 simplifies this by specifying that all interface signals are sampled on the rising edge of PCLK.

The APB2 specification requires a transaction to be completed in the ACCESS phase, i.e., the peripheral must provide valid read data before the rising edge that ends the ACCESS phase, and the transfer finishes at the end of cycle 2. There is no PREADY signal through which the peripheral can request more time.

APB3 introduces PREADY to support slower operation. When slave data is not available yet, it can keep PREADY low, which tells the master not to complete the transfer yet. Once data becomes available, the slave asserts PREADY along with the requested data.

PREADY high during the ACCESS phase allows the transfer to complete at the next rising edge of PCLK. However, whether it is successful cannot be detected from data or PREADY alone.

Hence, APB3 also includes PSLVERR, which is sampled when PSEL, PENABLE, and PREADY are all high. PSLVERR high indicates an error response but does not define whether the DUT state was updated during this erroneous transfer.

The peripheral needs to implement a strategy to handle erroneous transfers, for example, checking the request first, rejecting it, and leaving the target register unchanged.

For an ordinary 32-bit register, an APB3 write updates all four bytes. So, if we wish to update just one byte while keeping the rest unchanged, we need to read the register contents, update the necessary position, and write the new data back to the register.

APB4 introduces PSTRB, which allows a supporting peripheral to selectively update the required bytes, avoiding writing stale values into unselected bytes.

APB4 also introduces protection attributes, allowing peripheral or interconnect logic to reject a non-secure write to a secure-only register. So, APB2 standardizes a single clock edge for transactions, APB3 introduces wait states for slow peripherals and a way to convey successful or unsuccessful transfers, and APB4 allows byte-controlled writes as well as protection attributes.