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The full FPGA & VLSI curriculum
38 courses across 6 learning paths.
Certificate includedLifetime access
All courses38 courses
Foundation Series 6: Vivado Automation with TCL
Automate Vivado projects, simulations, and FPGA builds.
VerificationBestseller
Verification Series 9 : Functional & Timing GLS with Vivado
Verify netlists with functional and timing GLS in Vivado.
FoundationBestseller
Foundation Series 5: Prompt Engineering for RTL Verification Engineers
Use structured AI prompts for RTL verification workflows.
FoundationBestseller
Foundation Series 4: GIT for FPGA Engineer
Manage RTL projects with Git, GitHub, and CI workflows.
CommunicationBestseller
Communication Series P6 : PCI Express (PCIe) Physical Layer Foundation
Understand PCIe physical layers, LTSSM, and link training.
CommunicationBestseller
Communication Series P5 : Legacy PCI Expansion bus architecture
Learn PCI bus architecture and design PCI logic in Verilog.
DesignBestseller
Design Series P5 : Clock Domain Crossing(CDC) essentials with Vivado 2024
Analyze clock domain crossings and synchronizers in Vivado.
VerificationBestseller
Verification Series 8 : Code Coverage essentials with Vivado 2024
Measure RTL code coverage and close gaps in Vivado.
CommunicationBestseller
Communication Series P4 : Building SDRAM controller in Verilog
Build and verify an SDRAM controller in Verilog.
DesignBestseller
Design Series P4 : Static Timing Analysis(STA) with Vivado 2024
Analyze setup, hold, and timing constraints in Vivado.
DesignBestseller
Design Series P3 : 50 Days of Verilog RTL
Build Verilog RTL skills through 50 practical design topics.
DesignBestseller
Design Series P2 : Verilog Lint Essentials
Improve Verilog RTL quality with practical linting rules.
ProcessorBestseller
Processor Series 1: Building Very Small Instruction Processor
Build a custom Verilog processor with the VSIP architecture.
Bestseller
Verification Challenge P1 : SystemVerilog Coding
Practice SystemVerilog coding for verification interviews.
FoundationBestseller
Foundation Series 3: TCL fundamentals
Learn Tcl scripting for VLSI and EDA automation.
Bestseller
Communication Series Q2: AXI Lite Quiz
Test AXI-Lite concepts and prepare for interviews.
DesignBestseller
Communication series P3 : AMBA AXI in Verilog
Design AXI4, AXI4-Lite, and AXI4-Stream RTL in Verilog.
Bestseller
Verification Series Q3: SystemVerilog Quiz
Test SystemVerilog concepts for verification interviews.
DesignBestseller
Communication series P2 : AMBA APB in Verilog
Design AMBA APB masters and slaves in Verilog.
DesignBestseller
Communication series P1 : UART, SPI and I2C in Verilog
Build UART, SPI, and I2C controllers in Verilog.
PyUVMBestseller
PyUVM Series 1: Python Fundamentals
Learn Python fundamentals for VLSI and RTL verification.
PyUVMBestseller
PyUVM Series 2: Understanding COCOTB
Verify RTL with legacy cocotb 1.x Python testbenches.
PyUVMBestseller
PyUVM Series 3: Python OOPs Basics
Build reusable RTL verification components with Python OOP.
PyUVMBestseller
PyUVM Series 4: Python OOPs Projects
Verify RTL with reusable Python OOP testbench projects.
VerificationBestseller
Verification Series 1: Fundamentals of SystemVerilog
Build SystemVerilog skills for layered RTL testbenches.
VerificationBestseller
Verification Series 2: SystemVerilog Projects
Verify RTL blocks and protocols with SystemVerilog projects.
VerificationBestseller
Verification Series 3: UVM Fundamentals
Build reusable RTL verification environments with UVM.
VerificationBestseller
Verification Series 4: UVM Projects
Apply UVM to practical RTL block and protocol verification.
VerificationBestseller
Verification Series 6: SystemVerilog Functional Coverage
Model and measure functional coverage with SystemVerilog.
VerificationBestseller
Verification Series 7: SystemVerilog Assertions
Write SystemVerilog assertions to verify RTL behavior.
FoundationBestseller
Foundation Series 1: Crafting a Strong VLSI Engineer Resume
Build an ATS-friendly resume for VLSI engineering roles.
FoundationBestseller
Foundation Series 2: Essential Front-end VLSI skills
Explore essential skills for VLSI design and verification.