Communication Series P6 : PCIe PIPE
7 skills you'll walk away with
42 items across 8 sections
Know what you're signing up for
Requirements
- Understanding of Verilog & Basics of PCIe PHY
Who this course is for
- RTL and FPGA engineers who want to understand how a PCIe MAC controls its PHY.
- Verification engineers building tests for PCIe link training and PIPE control sequences.
- Engineers who have studied PCIe LTSSM states but want to connect those states to actual PIPE signals and RTL.
Why this course exists
A PCIe link depends on close coordination between the MAC and the PHY. The PIPE interface carries data between them and lets the MAC request PHY operations such as power state changes, electrical idle, rate changes, receiver detection, and loopback. Understanding the signals individually is straightforward; understanding when to assert them, what to wait for, and how they relate to LTSSM states takes more work. This course teaches those control sequences through a hands-on Gen1/Gen2, single-lane Verilog project. You will build separate RTL blocks for P0/P0s/P1 power control, transmit and receive electrical idle, rate changes, receiver detection, and loopback. You will then connect them into a PIPE controller and study how requests, PhyStatus, RxStatus, and completion signals work together. By the end, you will be able to read a PIPE timing sequence and explain what the MAC requests, what the PHY performs, and what the LTSSM must confirm before moving on. The course focuses on the MAC–PHY control interface; it does not claim to build a complete PCIe controller or analog PHY.
What you should know going in
- Understanding of Verilog & Basics of PCIe PHY
Why this course exists
A PCIe link depends on close coordination between the MAC and the PHY. The PIPE interface carries data between them and lets the MAC request PHY operations such as power state changes, electrical idle, rate changes, receiver detection, and loopback. Understanding the signals individually is straightforward; understanding when to assert them, what to wait for, and how they relate to LTSSM states takes more work. This course teaches those control sequences through a hands-on Gen1/Gen2, single-lane Verilog project. You will build separate RTL blocks for P0/P0s/P1 power control, transmit and receive electrical idle, rate changes, receiver detection, and loopback. You will then connect them into a PIPE controller and study how requests, PhyStatus, RxStatus, and completion signals work together. By the end, you will be able to read a PIPE timing sequence and explain what the MAC requests, what the PHY performs, and what the LTSSM must confirm before moving on. The course focuses on the MAC–PHY control interface; it does not claim to build a complete PCIe controller or analog PHY.
Who this course is for
- RTL and FPGA engineers who want to understand how a PCIe MAC controls its PHY.
- Verification engineers building tests for PCIe link training and PIPE control sequences.
- Engineers who have studied PCIe LTSSM states but want to connect those states to actual PIPE signals and RTL.
Taught by Kumar Khandagle
Kumar Khandagle
Founder, Namaste FPGA · Mumbai, India
15 years of production silicon — from high-frequency trading on Xilinx Alveo, to India's indigenous MRI machine, to training engineers at Mumbai University. Top 1K instructor on Udemy. Every course here comes from work he's actually shipped.
What learners are saying
No reviews yet
Be the first to review this course.