Field notes from building silicon — design walkthroughs, verification deep-dives, and the hard-won details.
17 articlesacross 7 topics
We have a set of protocols for connecting to sensors most common one are UART, SPI, and I2C. Along with them, bus protocols such as APB, AXI, and AHB are also known to many developers. In fact, AXI is a standard way we interact with peripherals implemented in Xilinx FPGA logic.
The original APB specification uses PSTB as well as BCLK to capture signals. It allows write capture on the rising edge of PSTB, the falling edge of PSTB, or the rising edge of BCLK while PSTB is HIGH.
In PCIe Gen1 and Gen2, we often share three parameters from the MAC to the PHY to control the transmitter?s electrical output. These include TxMargin, TxDeemph, and TxSwing. Each performs a unique role.
Many LTSSM training substates use TS1 and TS2 Ordered Sets, but states such as Hot Reset and Loopback use only TS1. Loopback is a special PCIe state intended mainly for testing entire path. PCIe normally does not use Master/Slave terminology but the specs defines a Loopback Master and a Loopback Slave.
While working with PCIe PHY, which consists of PCS and PMA, if we are working on the FPGA side, we predominantly look at PCS, while PMA remains hidden from us. We only know that data from PCS will reach the serializer.
Agents can generate scripts that control the flow to meet our requirements, which could be as simple as achieving setup slack greater than 0 ns. They can run the design flow, generate timing reports, identify the worst paths, and try optimization strategies until they reach the specified goal or an attempt limit.
An interesting property of a shared bridge is that, as we add more and more peripherals, its overhead could actually be recovered through savings in the peripheral interfaces. At a certain peripheral count, APB with a bridge may consume the same or less number of LUTs as AXI4-Lite. Let us explore the peripheral count at which both consume the same amount of LUTs.
When we work with EDA tools like Vivado, we often need to improve code readability. #1] Complex code can be placed in a separate file and included wherever required, allowing us to focus on the main design - Directives #2]We may also want to control how the tool handles a specific portion of code - Pragma #3] Override its default implementation choices - Attributes
One difficulty we face while testing a PCIe PIPE wrapper is DUT generates PIPE outputs based on the stimulus we apply, but we also need to mimic behavior of PCIe PHY. Since PHY implementations are vendor-specific, we often generate their responses manually in the testbench. However, generating both the stimulus and the expected PHY responses manually can overlook incorrect DUT behavior.
When we build AXI peripherals, we frequently need storage for control information or data. We have multiple alternatives for storage it could either be registers to store individual words, or we could adopt a FIFO or RAM inside the peripheral.
When we work with Tcl, whenever we add new files to different Vivado filesets, such as Design Sources or Simulation Sources, we need to update the compile order. Whether we add a single file or multiple files, Vivado analyzes the sources to identify the hierarchy, understand how different Verilog modules are connected, and determine the appropriate compilation order.
Most of the time, we wonder: if APB and AXI4-Lite can both meet low-bandwidth requirements, why do we still need to learn APB? Why shouldn?t we just stick to AXI4-Lite?