Use of Checker in SystemVerilog Assertions
Checkers are special verification-related constructs introduced in IEEE 1800-2012 to package assertions inside them.
The Journal
Quick Takes on RTL Design, Verification, Protocols and Processor related Constructs
Field notes from building silicon — design walkthroughs, verification deep-dives, and the hard-won details.
375 articlesacross 10 topics
Adding Debug core to Processor RTL Part 1: Debug core ports
Most of us design processor from scratch while learning computer architecture, which includes data and instruction memory, ALU, program counter, and control path performing sequential execution of fetch, decode, and execute. However, very few of us adopt a debug core inside the processor RTL. With a debug core, we can halt the CPU at any moment and inspect registers or memory at that instant. This gives the capability to inspect failures even if the CPU is stuck in an infinite loop. Another important advantage is ecosystem compatibility. Modern debugging tools such as GDB, OpenOCD, IDE debuggers, RTOS-aware debuggers, and trace analyzers depend on hardware debug support.
How to Become an RTL Verification Engineer: Complete Beginner?s Guide
Let us cover how we can progressively learn everything required to become verif engg.
Vivado's RTL Linter: What's Still Missing in 2026
Vivado's inbuilt linter supports a wide variety of checks. These include width mismatch, mixing assignment operators within a single always block, misuse of clock and reset, latch inference due to incomplete if-else and case statements, multiple drivers, combinational loops, and signed-unsigned mismatch. In comparison, Verilator and commercial linters provide far more exhaustive checks than Vivado. Vivado is progressing well with the addition of new rules in every new release. However, there are still several important rules that we expect to see in future versions of Vivado.
Ways to build FSM (Moore or Mealy) from scratch
FSMs need to handle three things: reset detection, next state prediction based on current state and input, and output prediction. Output prediction either depends on both current state and input (Mealy) or only on current state (Moore). This is why an FSM is built around three subsystems ? reset decoder, next state decoder, and output decoder.
Building SDRAM controller initialization logic in Verilog
SDRAM won't be immediately ready to use after power up because the internal cells used to store bits may have undefined state and configuration settings have not been provided yet. So before any real read/write operations, the memory controller has to walk it through a fixed initialization sequence defined by JEDEC. After power and clock become stable, we wait for a power-up delay of 100 to 200 microseconds, which gives the chip enough time to settle so the rest of the steps behave predictably.
Moore vs Mealy FSM: Key Differences and Conversions
We have two ways or models to implement FSM ? it could either be Moore or Mealy. Moore output depends only on the current state, so when we build a Moore FSM in Verilog we simply check which state we are in and assign a value for the output in that state, independent of the value of the current input. Mealy output depends on both the current state as well as the current value of the input, so when we build the output decoder logic we need to check which state we are in, then check the value of the input, after which we can decide what the output value will be.
Building Legacy PCI bus from scratch in verilog.
PCI uses a shared bus to exchange data between the host and peripherals . The problem with a shared bus is that any master device could initiate a transaction, so if multiple masters try to access the bus at the same time we will have contention. To handle this, PCI uses a central arbiter (sitting in the host chipset) which grants the bus to one master at a time using REQ#/GNT# signal pairs. Let us build PCI target in verilog. We can divide entire pci core into two parts one that is build in verilog and other handle analog side of pci.
What Time Borrowing means in Static Timing Analysis
STA violations can be solved with a multitude of strategies. We already covered forward and backward retiming, which is first steps to try out. Other than forward retiming, which uses registers to reduce delays and improve max operating frequency, pipelining also uses registers to divide delays into shorter ones to improve frequency. Both look similar, but there exists a subtle difference between them: retiming reduces delays by moving existing registers to improve frequency, while pipelining adds new registers to improve timings.
Why Modeling Styles in Verilog Often Borrow Constructs from Each Other ?
We often say we have four different ways to build the same system viz. Switch, Gate-level, Behavioral and Structural Modeling. Each modeling style utilizes different constructs to build the system e.g. Switch will use switch primitives, Gate-level will use logic gate primitives, Behavioral will use procedural assignment and continuous assignment if required, Structural will mostly deal with instantiation of components and sometimes include primitives or continuous assignment ? so we don't have clear restrictions on which constructs to use for a specific modeling style.
Why Slack computation on asynchronous CDC paths is not accurate and cannot be trusted
Slack is the difference between required time and arrival time. If this is greater than or equal to zero we have positive slack or no timing violation, but if slack itself is negative then we have violations in the timing path.
YML file role in CI/CD pipeline
While working with CI/CD pipelines, we need to perform different static as well as dynamic checks. Each step in flow consumes a different amount of time.