PCIe PIPE implementation

While working with PCIe PHY, which consists of PCS and PMA, if we are working on the FPGA side, we predominantly look at PCS, while PMA remains hidden from us. We only know that data from PCS will reach the serializer.

In PCS, we mainly focus on generating and receiving data bytes and identifying whether they are data or control characters. Most PMA control operations, such as speed change, PHY power mode change, Tx and Rx Electrical Idle, receiver detection, loopback, and Rx Standby, remain hidden or abstract to us. Therefore, we missed inside the PHY.

Since we focus on PCS, our agenda is mainly the Tx and Rx data paths rather than PHY control operations, which are part of PMA and are mostly initiated through the PIPE interface.

Let us consider the TX side. The MAC or LTSSM decides the control operation of the PHY. The operation could include data or control character transmission, placing the transmitter into electrical idle, detecting whether a receiver is connected, changing the link speed, changing the PHY power state, or requesting loopback.

Both data and control operations move through PIPE and reach the PHY. Based on the control signals, the PHY decides whether it is normal data transmission, link training, or a PHY mode change operation.

If its PHY mode change, we need to generate control signals. PIPE will verify that the mandatory requirements are met before sending the request to the PHY.

Assume we are doing power change, e.g., going from L0 to L1 may require changing the PHY power state from P0 to a lower-power state. It could also include a rate change, such as changing from Gen1 to Gen2, receiver detection, loopback, etc. If we keep our design simple and assign priority such as rate → power → receiver detection → loopback, then we need to verify that no higher-priority task is already queued. We also need to ensure that all mandatory rules are followed. e.g., specs may allow us to move from P0 to another lower-power state, but may restrict direct transitions between low-power states. We also need to ensure that loopback is not scheduled and that Tx is idle.

Once we confirm that no higher-priority operation is queued and all required rules are followed, the request goes to the control path. if control FSM is ready to initiate a new operation. Then we generate necessary control signals, and forward the request to the PHY.

The PHY then changes its mode and returns status to us, which we need to forward to the MAC because the MAC or LTSSM initiated the power-change operation.

Since this is handled entirely by PIPE, we do not discuss much of it while learning PCS. We decided to bring these PIPE details to everyone so that FPGA developers can understand the internal PMA control operations, which most of the time remain abstract because we mainly focus on PCS.