Shallow vs. Deep Copy in Pyhton Testbench Environments
Testbench environments can be of two types: in-order execution and out-of-order execution.
The Journal
Quick Takes on RTL Design, Verification, Protocols and Processor related Constructs
Field notes from building silicon — design walkthroughs, verification deep-dives, and the hard-won details.
17 articlesacross 7 topics
Async vs Sync in COCOTB/Python
Verification environments demand precise control over test execution. Python's async and sync functions become your conductors, ensuring tasks play their parts in perfect harmony.
What's New in Namaste FPGA V6? A Complete Walkthrough
Explore Namaste FPGA V6? from personalized course recommendations and redesigned pages to an improved learning experience. Learn how to resume lessons, use autoplay and keyboard controls, track your progress, and access certificates and payment history.
Vivado's RTL Linter: What's Still Missing in 2026
Vivado's inbuilt linter supports a wide variety of checks. These include width mismatch, mixing assignment operators within a single always block, misuse of clock and reset, latch inference due to incomplete if-else and case statements, multiple drivers, combinational loops, and signed-unsigned mismatch. In comparison, Verilator and commercial linters provide far more exhaustive checks than Vivado. Vivado is progressing well with the addition of new rules in every new release. However, there are still several important rules that we expect to see in future versions of Vivado.
Scope in SystemVerilog & UVM and role of ref
Scope defines the region where functions, tasks, and variables are declared, determining where they can be accessed and modified in the code. Scope also dictates the visibility of variables, tasks, and functions. There are three possible scopes: Local, Global, and Caller.
Divergence, Convergence & Reconvergence in CDC ?
A) Divergence (or fan-out) in Clock Domain Crossing (CDC) happens when a single signal in the single clock domain splits into multiple independent paths before crossing to the destination domain through separate synchronizers.
Surprise Rewards Coming for Namaste FPGA Learners!
At Namaste FPGA, we believe that consistent learning and dedication deserve to be celebrated. Your effort, curiosity, and persistence are what make this community so special. To honor and encourage this spirit, we are excited to announce something new starting September 2025 ? Surprise Merchandise and Course Rewards for the Top 10 learners of the month!