Divergence, Convergence & Reconvergence in CDC ?

A) Divergence (or fan-out) in Clock Domain Crossing (CDC) happens when a single signal in the single clock domain splits into multiple independent paths before crossing to the destination domain through separate synchronizers.

We have two situations here. If the signals are never merged and each follows its own independent logic path in the destination domain, then there is no collective data incoherency, so the best strategy is simply to use a standard flop synchronizer on each independent path.

But if those signals later merge again in the destination domain, then flip-flop synchronizers alone are not enough, because each path can arrive at different times; in that case we need to adopt same strategies that prevent reconvergence hazards, described next.

B) Reconvergence happens when multiple signals from one clock domain take different paths, then each crosses the boundary through its own synchronizer, and finally they are combined again (for example, ANDed, ORed, compared, decoded) by combinational logic in the destination domain to produce some output.

Reconvergence can also happen when two signals are generated in the same clock domain but have different path delays and we merge them in combinational logic; this local reconvergence can still cause a glitch if the logic is sensitive to momentary mismatches. Most preferred approach here is to register output in same clock domain before crossing.

While in case of signal merging in different domain startegies vary based on source and destination clock frequencies. Most common approach is to treat the related signals as one unit: combine them into a bus in the source domain, freeze that bus so it stays stable, and send a single control (valid/ready style) across. Then, depending on the frequency relationship between the two domains, we choose the mechanism. If the source clock is slower than the destination clock, we can hold the grouped signals stable and send a valid pulse that the destination synchronizes and uses to latch the whole bus at once, which is basically a lightweight handshake. If we need stronger guarantee or bi-directional control, we use a full request/acknowledge handshake.

If the source clock is faster than the destination clock, we should use an asynchronous FIFO to safely transfer the merged data, because the FIFO can absorb rate differences without losing information. If both clocks are frequency-related (for example derived from the same PLL with known phase) then we may be able to treat that crossing with normal STA-based timing techniques instead of generic asynchronous CDC.

A more detailed coding walkthrough and demo of these techniques will be covered in the next post.