if APB and AXI4-Lite both are low-bandwidth then why we use APB ?
Most of the time, we wonder: if APB and AXI4-Lite can both meet low-bandwidth requirements, why do we still need to learn APB? Why shouldn’t we just stick to AXI4-Lite?
Bandwidth represents only one side of the triangle. The second side represents hardware cost, which depends on factors such as resource consumption and the availability of existing IPs. The third side represents verification effort.
Our goal is to always reach balance between three. APB uses a shared bus for read and write hence only one transfer can occur at a time making half duplex. AXI4-Lite has independent read and write channels, allowing both to occure simultaneously making it full duplex.
AXI4-Lite can therefore achieve higher throughput than APB. This gives AXI4-Lite an advantage on the bandwidth side of the triangle.
If we compare interface signal counts, a typical APB4 interface uses 110 signal bits, while AXI4-Lite uses 154. Within an FPGA, these are usually internal connections increasing routing demand and contribute to congestion and LUT consumptions.
APB4 therefore often has an advantage in peripheral-interface simplicity and resource consumption.
If you have used Xilinx FPGAs, you will have seen both soft and hard processor interfaces use AXI. To connect an APB peripheral to an AXI interface, we need a bridge, which adds resource overhead. When several APB peripherals share one bridge, that overhead is distributed among them. This can make an APB subsystem competitive with an AXI4-Lite subsystem.
If we already have suitable APB IPs, reusing them can also reduce development and verification costs compared with rebuilding their interfaces for AXI4-Lite. This often put APB ahead of AXI on the hardware and IP integration side of the triangle.
APB uses a simple transaction sequence: SETUP followed by ACCESS. The ACCESS phase can include wait states, and the transfer completes when PSEL, PENABLE, and PREADY are all high. Transactions follow a predictable sequence, so verification generally involves fewer cases. In AXI4-Lite writes, the address can arrive first, the data can arrive first, or both can arrive together. Independent channel handshakes, backpressure, responses, and overlapping read and write transactions introduce additional verification cases. AXI4-Lite peripheral verification therefore typically requires more effort than APB verification. APB has an advantage on this third side of the triangle, helping explain why APB peripherals remain useful even in systems with native AXI support.
Hence, Understanding both prepares us for situations where we need to use either protocol or combine them.
