Bus Vs Communication Protocols

We have a set of protocols for connecting to sensors most common one are UART, SPI, and I2C.

Along with them, bus protocols such as APB, AXI, and AHB are also known to many developers. In fact, AXI is a standard way we interact with peripherals implemented in Xilinx FPGA logic.

These fall into two subcategories: serial communication interfaces and internal bus protocols. Each one solves different kinds of challenges, although SPI and I2C are also called serial bus protocols.

Serial communication interfaces are meant to communicate data with a small number of pins, as each new pin can add extra hardware cost, space, and power consumption. Hence, an important goal of these interfaces is to communicate data with fewer pins.

That means transferring data from a sensor consumes multiple bit periods. These interfaces prioritize communicating data between devices with fewer physical connections rather than providing wide, parallel register reads or writes.

UART consumes 10 bit periods to transmit an 8-bit data byte with one start bit, no parity, and one stop bit. Likewise, SPI and I2C consume multiple clock cycles to communicate data.

Each of them has a unique way to exchange control and data information. For example, UART carries framing information and data on the same line. To start transmitting a character, the data pin goes low, which marks the start of transmission, followed by the actual data and then the stop bit. T he start bit identifies the beginning of a character; commands identifying the type of operation must be defined by software and transmitted as data.

SPI uses CS to choose a peripheral and independent MOSI and MISO lines for data flowing in opposite directions. Read or write operations are identified through the peripheral’s command format. I2C communicates the address of the peripheral and a read/write bit, followed by data and acknowledgement bits. With these approaches, we can communicate data and control information with typically two to four signal pins, excluding power, ground, and optional signals.

The problem with using serial transactions for every processor access is that the processor may need frequent writes and reads. If we perform these accesses through serial communication interfaces, we may need to wait for multiple bit periods to perform a single write or read.

Hence, if Zynq wants to read previously captured SPI ADC data from an AXI-connected controller in FPGA logic, Zynq initiates an AXI read. The controller IP then accesses the register holding the sensor data and returns that data through AXI. Within the chip, these bus connections use routing resources rather than external package pins, so multiple data bits are transferred in parallel. We can therefore complete a register read in a few cycles.

Hence, when we work with a processor, its internal bus connects to controller IPs that act as bus peripherals.