Verification Series 9 : Functional & Timing GLS with Vivado

Before deploying any FPGA or ASIC design to hardware, verifying only the RTL functionality is no longer sufficient. Synthesis, optimization, placement, routing, and real hardware delays can introduce behaviors that are impossible to observe during traditional RTL simulation. Gate-Level Simulation (GLS) bridges this gap by allowing engineers to verify the synthesized and implemented design under realistic hardware conditions, making it an essential skill for modern RTL and verification engineers. This course provides a comprehensive and practical introduction to Functional and Timing Gate-Level Simulation, beginning with the motivation for GLS and its role in the digital design flow. You will learn how behavioral simulation differs from gate-level simulation, understand synthesized netlists, and clearly distinguish between Functional GLS and Timing GLS. The course explains how synthesis transforms RTL into technology-specific primitives and how gate-level simulation verifies that synthesis has preserved the intended functionality. You will explore the behavior of unknown (X) values in digital systems, including X propagation, X optimism, and X pessimism, and understand why these concepts are critical when debugging synthesized hardware. The course demonstrates how unknown values spread through combinational logic, finite state machines, memories, enable signals, and clock-gating circuits, while introducing systematic methodologies for tracing X values back to their true source. A significant portion of the course focuses on practical Functional GLS debugging techniques. You will learn reset coverage analysis, structured X propagation debugging, and methods for distinguishing between real hardware issues and simulation artifacts. Rather than relying on trial-and-error debugging, the course presents repeatable workflows used by experienced verification engineers to identify and resolve functional issues efficiently. The course then transitions into Timing Gate-Level Simulation, introducing the Standard Delay Format (SDF) file, timing annotation, SDF structure, minimum/typical/maximum delays, Process-Voltage-Temperature (PVT) variations, synthesis versus implementation SDF files, and the timing checks that enable realistic hardware verification. You will gain a detailed understanding of setup, hold, recovery, removal, clock period, and pulse-width checks, along with the Verilog timing system tasks that perform these checks automatically during simulation. Finally, the course concludes with a complete Timing GLS case study based on a Clock Domain Crossing (CDC) design using a two-flop synchronizer. Through this practical example, you will learn how to build a Timing GLS testbench, analyze waveforms with real hardware delays, interpret timing violation reports, perform root-cause analysis, and systematically debug setup and hold violations. By the end of the course, you will possess a complete understanding of Functional and Timing Gate-Level Simulation, enabling you to confidently verify synthesized hardware, debug complex timing issues, and apply industry-standard GLS methodologies in professional FPGA and ASIC verification projects.