Communication Series P6 : PCI Express (PCIe) Physical Layer Foundation

This advanced PCI Express (PCIe) course is designed to give VLSI engineers a complete and implementation-ready understanding of modern PCIe link architecture, beginning with the structural hierarchy of Root Complexes, Switch fabrics, and Endpoints across multiple progressively detailed modules. The course provides conceptual overviews of the Transaction Layer and Data Link Layer—sufficient for framing packet flow, credit management, and DLLPs—while placing its primary emphasis on the Physical Layer, where PCIe link training, electrical initialization, bit-level synchronization, and ordered-sequence–based negotiation actually occur. A multi-part exploration of the Physical Layer walks learners through the PMA (electrical signaling, serialization, symbol timing, receiver detection) and PCS (8b/10b or 128b/130b encoding, scrambling, lane alignment, SKP insertion, and byte-wise symbol processing) before presenting a full integrated understanding of PHY sub-block operation. From this foundation, the course introduces the Link Training and Status State Machine (LTSSM) in depth, explaining why LTSSM is essential, how it governs link initialization, and how resets influence state advancement. All PCIe resets—cold, warm, and hot—are described rigorously, along with the conditions under which link training must be performed and how physical link conditions drive transitions between Detect, Polling, Configuration, L0, Compliance, and power-down states. The core of the program focuses on building PCIe Physical Layer functionality in synthesizable Verilog. Learners construct key sub-blocks such as the Ordered Set Generator, Equalization Logic, TS1/TS2 formation, control-character handling, and training-sequence emission. They then implement the TX-side LTSSM, creating the logic that sequences physical-layer states and transmits training patterns reliably; followed by the RX-side LTSSM, which includes Detect logic, Polling logic, Ordered Sequence decoding, symbol lock via comma detection, lane and link negotiation, and complete bring-up behavior. The course concludes with the creation of an RX Packet Parser that interprets incoming symbols and ordered sets, forming the bridge between the Physical Layer and the upper layers. By the end of the course, engineers will not only understand PCIe hierarchy and layered architecture but will also possess the skills to architect, implement, and verify the PCIe Physical Layer and LTSSM in Verilog, including critical components such as OS generation, equalization logic, TX/RX LTSSM state machines, and PHY-level packet parsing, enabling real-world integration into SoC and high-speed interface designs.