Verification Series 6: SystemVerilog Functional Coverage

The verification process is becoming complex and time-consuming day by day with advances in the Hardware Description Languages and IPs. HDL has added capabilities that allow the engineer to Design and write Testbench for complex systems. But verifying designer intent and deciding set of right stimuli to meet the Verification plan is not always easy with HDL. Hence System Verilog introduces assertions and Coverage to fulfill this requirement by adding independent constructs to language. SystemVerilog assertions allow us to verify Designer intent in both Temporal and Non-Temporal domains. Functional Coverage act like feedback for the stimulus we are sending to DUT so that we could reach to best stimulus for verifying the plan in the least amount of time. This course covers the fundamentals of different types of bins viz, Implicit bins, Explicit bins, Wildcard bins, Ignore bins, default bins, illegal bins with a demonstration of each of them in RTL. Fundamentals of Cover group, Reusable Covergroup, and different Sampling methods viz. event, sample() method, and User-defined Sample Method are discussed in detail. Functional Coverage gives us the ability to verify the relation between the signal by using Cross Coverage and detailed discussion on Cross coverage with different combination filtering strategies are covered in detail. Finally, Transition bins provide temporal abilities to Functional Coverage is also discussed in detail with projects demonstrating the usage of Functional Coverage in Verilog and SystemVerilog Testbench.