AS
Aviral Singhal
5 months ago
Rated this course 5 out of 5.
Verification Challenge P1 : SystemVerilog Coding
BestsellerSubtitlesEnglish
What you'll learn
1 skills you'll walk away with
SystemVerilog Interview Preparation
Course content
3 items across 1 section
3 assignments1 hours total
Course details
Know what you're signing up for
Requirements
- Fundamentals of SystemVerilog.
Who this course is for
- Anyone preparing for Front end Verification role.
Why this course exists
Test your Understanding of SystemVerilog concepts.
Requirements
What you should know going in
- Fundamentals of SystemVerilog.
Description
Why this course exists
Test your Understanding of SystemVerilog concepts.
Who it's for
Who this course is for
- Anyone preparing for Front end Verification role.
Instructor
Taught by Kumar Khandagle
KK
Kumar Khandagle
Founder, Namaste FPGA · Mumbai, India
4.5 instructor rating60,000+ engineers34 courses15+ yrs silicon
15 years of production silicon — from high-frequency trading on Xilinx Alveo, to India's indigenous MRI machine, to training engineers at Mumbai University. Top 1K instructor on Udemy. Every course here comes from work he's actually shipped.
Reviews
What learners are saying
4.8
11 reviews
SA
Sharon anto
9 months ago
Very useful
AR
Ankith Rao
1 year ago
Great learning experience
JP
Jayaraman r p
1 year ago
Quality content at affordable price
PP
Ponnada Pavani
1 year ago
yes ,i like it
KC
KURUTI CHANDU
1 year ago
Rated this course 5 out of 5.
TK
Thumarada Santhosh Kumar
1 year ago
It is useful for ece students to practice the system verilog codes
TD
Tran Tuan Dat
2 years ago
Rated this course 5 out of 5.
R
Rushik
2 years ago
Rated this course 5 out of 5.
SS
SHUBHANGI GAJANAN SARDAR
2 years ago
great