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Communication series P3 : AMBA AXI in Verilog

4.8(12 reviews)9 hours128 items Certificate
BestsellerSubtitlesEnglish
What you'll learn

4 skills you'll walk away with

Course content

128 items across 9 sections

105 lectures9 hours total
Course details

Know what you're signing up for

Requirements
  • Fundamentals of Digital Electronics, Verilog.
Who this course is for
  • A VLSI engineer is interested in constructing AXI peripheral for SoC.
Why this course exists

Unlock the essentials of AXI protocol with our hands-on course designed to give you a deep understanding of AXI fundamentals in Verilog. This course is structured to be 95% coding and 5% theory, ensuring you gain practical, real-world skills. You'll dive into the different signals of AXI Stream, AXI Lite, and AXI Full interfaces, and learn to build AXI Stream, AXI Lite, and AXI Full Master and Slave components from scratch. Implement different burst modes, probe and verify AXI transactions using the AXI protocol checker, and build advanced components such as AXI Stream FIFOs, arbiters, and AXI Lite GPIO from the ground up. With extensive coding practice and essential theoretical insights, this course equips you with the knowledge and skills needed to excel in design and verification roles, preparing you to ace any interview in the field. Enroll now and take the first step towards mastering AXI in Verilog!

Requirements

What you should know going in

  • Fundamentals of Digital Electronics, Verilog.
Description

Why this course exists

Unlock the essentials of AXI protocol with our hands-on course designed to give you a deep understanding of AXI fundamentals in Verilog. This course is structured to be 95% coding and 5% theory, ensuring you gain practical, real-world skills. You'll dive into the different signals of AXI Stream, AXI Lite, and AXI Full interfaces, and learn to build AXI Stream, AXI Lite, and AXI Full Master and Slave components from scratch. Implement different burst modes, probe and verify AXI transactions using the AXI protocol checker, and build advanced components such as AXI Stream FIFOs, arbiters, and AXI Lite GPIO from the ground up. With extensive coding practice and essential theoretical insights, this course equips you with the knowledge and skills needed to excel in design and verification roles, preparing you to ace any interview in the field. Enroll now and take the first step towards mastering AXI in Verilog!

Who it's for

Who this course is for

  • A VLSI engineer is interested in constructing AXI peripheral for SoC.
Instructor

Taught by Kumar Khandagle

KK

Kumar Khandagle

Founder, Namaste FPGA · Mumbai, India

4.5 instructor rating60,000+ engineers34 courses15+ yrs silicon

15 years of production silicon — from high-frequency trading on Xilinx Alveo, to India's indigenous MRI machine, to training engineers at Mumbai University. Top 1K instructor on Udemy. Every course here comes from work he's actually shipped.

Reviews

What learners are saying

4.8
12 reviews
RJ
Ruthvik B J
4 months ago

Rated this course 5 out of 5.

DJ
Deepak Jain
5 months ago

Rated this course 5 out of 5.

N
noman
6 months ago

Rated this course 5 out of 5.

PS
Pradeep Sangala
10 months ago

Rated this course 5 out of 5.

NV
Nikunj Vaghani
10 months ago

Rated this course 5 out of 5.

SJ
Sudheer J
12 months ago

need more used cases on pipeline with burst

HD
HARSHITH GOWDA B D
1 year ago

Thank you so much sir , it helping a lot to my project , plese add the interleaving and outstanding feature and pipeline.......

RE
Roshan Ekte
1 year ago

all axi design are without pipeline code are non-synthesizable use initial block in design

VV
Vinayak Vakare
1 year ago

Simple explanation and expalined in detailed

PR
Prajwal Ramakrishna
1 year ago

Very detailed explanation.....

$ 6.99One-time payment