Rated this course 5 out of 5.
AMBA AXI in Verilog
4 skills you'll walk away with
128 items across 9 sections
Know what you're signing up for
Requirements
- Fundamentals of Digital Electronics, Verilog.
Who this course is for
- A VLSI engineer is interested in constructing AXI peripheral for SoC.
Why this course exists
Unlock the essentials of AXI protocol with our hands-on course designed to give you a deep understanding of AXI fundamentals in Verilog. This course is structured to be 95% coding and 5% theory, ensuring you gain practical, real-world skills. You'll dive into the different signals of AXI Stream, AXI Lite, and AXI Full interfaces, and learn to build AXI Stream, AXI Lite, and AXI Full Master and Slave components from scratch. Implement different burst modes, probe and verify AXI transactions using the AXI protocol checker, and build advanced components such as AXI Stream FIFOs, arbiters, and AXI Lite GPIO from the ground up. With extensive coding practice and essential theoretical insights, this course equips you with the knowledge and skills needed to excel in design and verification roles, preparing you to ace any interview in the field. Enroll now and take the first step towards mastering AXI in Verilog!
What you should know going in
- Fundamentals of Digital Electronics, Verilog.
Why this course exists
Unlock the essentials of AXI protocol with our hands-on course designed to give you a deep understanding of AXI fundamentals in Verilog. This course is structured to be 95% coding and 5% theory, ensuring you gain practical, real-world skills. You'll dive into the different signals of AXI Stream, AXI Lite, and AXI Full interfaces, and learn to build AXI Stream, AXI Lite, and AXI Full Master and Slave components from scratch. Implement different burst modes, probe and verify AXI transactions using the AXI protocol checker, and build advanced components such as AXI Stream FIFOs, arbiters, and AXI Lite GPIO from the ground up. With extensive coding practice and essential theoretical insights, this course equips you with the knowledge and skills needed to excel in design and verification roles, preparing you to ace any interview in the field. Enroll now and take the first step towards mastering AXI in Verilog!
Who this course is for
- A VLSI engineer is interested in constructing AXI peripheral for SoC.
Taught by Kumar Khandagle
Kumar Khandagle
Founder, Namaste FPGA · Mumbai, India
15 years of production silicon — from high-frequency trading on Xilinx Alveo, to India's indigenous MRI machine, to training engineers at Mumbai University. Top 1K instructor on Udemy. Every course here comes from work he's actually shipped.
What learners are saying
Rated this course 5 out of 5.
Rated this course 5 out of 5.
Rated this course 5 out of 5.
Rated this course 5 out of 5.
need more used cases on pipeline with burst
Thank you so much sir , it helping a lot to my project , plese add the interleaving and outstanding feature and pipeline.......
all axi design are without pipeline code are non-synthesizable use initial block in design
Simple explanation and expalined in detailed
Very detailed explanation.....