imageNamaste FPGA
image
Paths
Courses
Reads
Ranks
Sign In
TracksHigh Speed Interfaces

Explore SDRAM and DDR3 controllers, legacy PCI architecture, PCIe physical-layer fundamentals, and the PIPE interface.

4live courseslive
22hof contentcontent
614engineers enrolledenrolled
4.7average rating
Begin with Building SDRAM controller in Verilog

The path

5 steps · 4 live5 steps · 4 live
Start here
1
Building SDRAM controller in Verilog 1 4h

Building SDRAM controller in Verilog

Explore initialization, mode registers, read/write operations, auto-refresh, and self-refresh.

4 hours4.0
(2)183 enrolled
2
Building DDR3 controller in Verilog 2
Schedule to be announced

Building DDR3 controller in Verilog

Dive into DDR3 architecture, command sequencing, timing requirements.

Part of this path
3
Legacy PCI Expansion bus architecture 3 5h

Legacy PCI Expansion bus architecture

Understand PCI bus operation, arbitration, transaction handling, and configuration space.

5 hours5.0
(3)190 enrolled
4
PCI Express (PCIe) Physical Layer Foundation 4 9h

PCI Express (PCIe) Physical Layer Foundation

Explore link training, LTSSM, ordered sets, equalization, and TX/RX RTL.

9 hours5.0
(5)208 enrolled
5
PCIe PIPE 5 4h

PCIe PIPE

Explore PHY power management, electrical idle, speed transitions, receiver detection.

4 hours33 enrolled
Path complete

Understand memory-controller operation and the architecture, timing, and link behaviour behind PCI and PCIe interfaces.