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TracksRTL Design

Start with Verilog and Vivado, practise RTL design, and strengthen your designs with lint, static timing analysis, and clock domain crossing techniques.

4live courseslive
18hof contentcontent
1.1kengineers enrolledenrolled
4.8average rating
Begin with 50 Days of Verilog RTL

The path

5 steps · 4 live5 steps · 4 live
1
Verilog for FPGA Engineer 1
Schedule to be announced

Verilog for FPGA Engineer

Getting Started with Verilog & Xilinx Vivado Design Suite

Part of this path
Start here
2
50 Days of Verilog RTL 2 5h

50 Days of Verilog RTL

Fast-paced mastery of common Verilog constructs.

5 hours4.8
(14)333 enrolled
3
Verilog Lint Essentials 3 4h

Verilog Lint Essentials

Master Verilog RTL linting to write clean, reliable, and synthesis-ready designs.

4 hours5.0
(5)198 enrolled
4
Static Timing Analysis(STA) with Vivado 2024 4 5h

Static Timing Analysis(STA) with Vivado 2024

Learn STA, setup/hold analysis, timing reports, and XDC constraints in Vivado.

5 hours4.6
(10)284 enrolled
5
Clock Domain Crossing(CDC) essentials with Vivado 2024 5 4h

Clock Domain Crossing(CDC) essentials with Vivado 2024

Explore metastability prevention, synchronization techniques, and Vivado CDC verification.

4 hours4.9
(8)256 enrolled
Path complete

Write and review RTL with a practical understanding of lint, timing constraints, and clock domain crossings.