Build from SystemVerilog to UVM testbenches and register models, then strengthen verification with assertions, functional coverage, code coverage, and gate-level simulation.
The path
9 steps · 9 live9 steps · 9 live
Fundamentals of SystemVerilog
Fundamentals of Systemverilog for building class based verification environment.
SystemVerilog Projects
Building verification environment for most common bus & communnication interfaces from scratch.
UVM Fundamentals
Fundamentals of UVM framework for building class based verification environment.
UVM Projects
Building UVM environment for most common bus & communnication interfaces from scratch.
SystemVerilog Functional Coverage
Fundamentals of SystemVerilog Functional Coverage from scratch.
Code Coverage essentials with Vivado 2024
Essentials of Statement, Branch, Condition, Toggle and FSM Coverage.
Functional & Timing GLS with Vivado
Verify synthesized hardware, debug timing violations, and master SDF-based Gate-Level Simulation
Build verification environments and use assertions, coverage, and simulation to check RTL behaviour.