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counter.sv

// 4-bit synchronous up-counter
module counter (
  input  logic       clk,
  input  logic       rst_n,
  output logic [3:0] count
);

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) count <= 4'b0;
    else        count <= count + 1'b1;

endmodule

play_circle Lesson 4 · Verilog Foundations

The VLSI curriculum, rebuilt from the ground up

FPGA & VLSI taught by the instructor 60,000+ engineers trust.

Verilog, SystemVerilog, UVM, PCIe, UART, SPI, I2C and RISC-V — structured as paths, not a catalog. Sharpened across 40+ Udemy courses.

4.5+13,800+ verified reviews

Kumar KhandagleTrainer @ NF · 60K+ on Udemy

counter.sv

// 4-bit up-counter
module counter (
  input  logic       clk,
  input  logic       rst_n,
  output logic [3:0] count
);
  always_ff @(posedge clk)
    count <= count + 1'b1;
endmodule

play_circle Lesson 4 · Verilog Foundations

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Flowchart based FSM Design Technique - SPI DAC

spi_dac.v

case (state)
    IDLE_DAC:
        state <= (!dac_init) ? INIT_DAC : FUNC_DAC;
    INIT_DAC:
        state <= (count == 31) ? FUNC_DAC : INIT_DAC;
    FUNC_DAC:
        state <= WRT_DAC;
    WRT_DAC:
        state <= (count == 31) ? IDLE_DAC : WRT_DAC;
endcase

What you'll take away

Use a case statement to implement FSM state-dependent behavior.
Use non-blocking assignments (<=) inside clocked always blocks.
Use a counter register to track the number of serial bits transmitted.
Use conditional operators or if-else statements to control state transitions based on flags such as dac_init and count.

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